Theos-Talk Archives (September 2002 Message tt00102)

September 13, 2002 
CPU Breakthrough: Chips Enter the Nano-Age 
By Loyd Case 
Today, we're seeing microprocessors from Intel and AMD using 0.13 micron 
process technology in high volume manufacturing. That's 130 nanometers. But 
just how big (or rather, how small) is 130 nanometers? According to Sunlin 
Chou, Intel's Senior Vice President for technology and manufacturing, the 
size of a typical virus is 100 nanometers. So today's manufacturing 
technology creates circuit traces approaching the size of the smallest living 
organism. 

90 Nanometer Process On Deck 
The next generation of process technology is 0.09 micron, or 90 nanometers. 
Sunlin Chou offered a heuristic of 100 nanometers as the breakpoint for 
defining nanotechnology. Anything smaller than 100 nanometers can be thought 
of as nanoscale. That's all well and good, but what does it actually mean? 
During the last day of IDF, Intel Fellow Mark Bohr offered some insight into 
the challenges and benefits of moving to smaller process technologies. 

Intel's current 0.13 micron manufacturing process is split between using 
200mm wafers and 300mm wafers. The company's upcoming 90nm process will use 
300mm wafers exclusively. Transistor gate lengths at 0.13 micron are less 
than 70nm, while the new process technology will have gate lengths of less 
than 50nm. 

Some additional key features of the 90nm process include: 

Strained silicon technology. Invidual layers of silicon atoms are deposited 
further apart. As subsequent layers are deposited, the atoms still tend to 
want to line up with the spread out atoms beneath. Thus, the crystal array is 
"strained" relative to previous generations. When the silicon lattice is 
spread apart, faster electron flows results. This can result in chips up to 
35% faster due to electron flows as much as 70% faster (source: IBM). 

Seven copper layers. This is one more metal layer than the current 0.13 
micron CPUs, but will improve logic circuit density. 
New, low-capacitance dielectric. The new, carbon-doped oxide will reduce 
capacitance by as much as 18%. This reduces current leakage and hence, chip 
power needs. 
The gate oxide for 90nm is only 1.2 nm thick -- roughly 5 atoms. 

Taken together, the result will be more dense, faster semiconductors that 
require lower voltages. The lower voltage will help keep the thermal power 
envelope to a manageable level, even at high clock rates. Bohr estimates that 
any large CPU built on Intel's 90nm process shouldn't have a thermal envelope 
higher than today's 0.13 micron CPUs. 

What's interesting is that as the process technologies scale down, the 
transistor gate lengths actually decrease at an accelerated rate, which can 
also help performance gains. 


Intel has been busy building test chips using the new process. Usually, the 
first type of chip to be built with a new logic process is an SRAM chip -- 
simple to lay out and its regularity helps to easily spot chip lithography 
issues. One example of this is a 52 megabit SRAM chip, which has 330 million 
transistors on a 100 square millimeter die. Although yields weren't 
discussed, Bohr mentioned that Intel had successfully manufactured perfect 
chips, with all 52 Mbits operational. Since SRAM is built in the same way as 
logic circuits, then it's a good bet that 90nm will work with CPUs. 
Additionally, today's CPUs often have substantial L2 cache sizes, and high 
density SRAM is useful here. 

Most of the development work for 90nm is being performed at Intel's 
Hillsborough, Oregon facility. In separate briefings, Intel has stressed that 
90nm is on track for deployment next year. The first processor to be built 
using the new process will be Prescott, an updated design of the Pentium 4 
microarchitecture. 

see full article with pictures at ; 
http://www.extremetech.com/article2/0,3973,533655,00.asp